The present invention relates to a capacitor structure for an integrated circuit and a method of fabrication thereof, with particular application to stacked planar capacitors for low leakage applications.
Modern integrated circuits, such as microprocessors, use numerous passive components such as resistors and capacitors. In one application, decoupling capacitors are used to reduce undesired noise signals from the power supply. For example, conventional embedded DRAM and decoupling capacitors typically utilize three dimensional structures to increase the surface area and to obtain large capacitance values. One method of adding decoupling capacitors to the microprocessor is by forming them on the package substrate. However, this method requires electrical routing between the capacitors and microprocessor, which increases thickness and cost of the package substrate. Furthermore, the electrical routing to the capacitors on the package increases inductance.
Decoupling capacitors have also been formed by on-chip techniques. For example, decoupling capacitors such as gate oxide capacitors or finger comb capacitors are often formed in the lower metal layers of the backend interconnect stack. However, the capacitance output of gate oxide or finger comb capacitors is limited by high voltage breakdown and layout factors.
Other methods include forming the decoupling capacitors in the passivation structure at the back end of line (BEOL). For example, US Pat. Pub. No. 2010/0224960 to Fischer et al. discloses the formation of fin like capacitors in BEOL. U.S. Pat. No. 5,583,359 to Ng et al. is another example of forming decoupling capacitors in the passivation structure in BEOL. However, these types of devices are prone to leakage and reliability issues due to the step height differences in the dielectric of the prior art capacitor structures, which makes multiple stacking of the same structure difficult. With regard to Ng, the dielectric between electrodes is not flat at the edges, which leads to current leakage and reliability issues. Current leakage necessitates an increase in dielectric thickness, which is undesirable for capacitance enhancement and higher chip area utilization.
Prior Art FIGS. 1-2 are transmission electron microscopic images of a stacked MIM capacitor including two planar capacitors that are stacked in BEOL, which include step height differences. As shown more clearly in FIG. 2, the step height at the edge can result in weak spots in the high k dielectric layer resulting in current leakage and reliability issues. At a minimum, capacitor structures including steps such as the type shown prevent aggressive EOT scaling and large area utilization. Moreover, the step height makes multiple stacking of the same structure difficult.